The present invention generally relates to semiconductor processing, and in particular to a method for improving a contact lithography process.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Present techniques in optical projection printing can resolve images of sub-micron when photoresists with good linewidth control are used. However, reflection of light from substrate/resist interfaces produce variations in light intensity and scattering of light in the resist during exposure, resulting in non-uniform photoresist linewidth upon development.
Constructive and destructive interference resulting from reflected light is particularly significant when monochromatic or quasi-monochromatic light is used for photoresist exposure. In such cases, the reflected light interferes with the incident light to form standing waves within the resist. In the case of highly reflective substrate regions, the problem is exacerbated since large amplitude standing waves create thin layers of underexposed resist at the wave minima. The underexposed layers can prevent complete resist development causing edge acuity problems in the resist profile. Antireflective coatings are known and used to mitigate the aforementioned problems, however, the use thereof presents additional problems such as, for example, introduction of particulate contamination, requirement of tight temperature tolerances during production, etc.
As contact dimensions shrink, charging damage during contact formation or during etching become more important. Charging damage can be caused by different contacts charging up due to non-uniformity in the etching plasma. If a sufficient voltage is attained between contact elements, a current can flow which damages the gate oxide of any transistors formed on the wafer being fabricated. This is known as electron shading. High density plasmas aggravate this effect by having a more severe xe2x80x9celectron shadingxe2x80x9d effect where the contact openings in the resist charge up with electrons. Since both the resist and the dielectric layer are being etched during contact/via etch are insulating, the only ways to equalize the charge imbalances is with current flow. An insulating anti-reflective coating is sometimes employed on top of the dielectric layer, under the resist. This layer is also insulating and does not improve the situation.
FIG. 1a illustrates a prior art wafer 10 including a substrate layer 12, an oxide layer 14 disposed above the substrate layer 12 and a photoresist layer 16 disposed above the oxide layer 14. A plurality of features 15 have been etched through the resist layer 16 and the oxide layer 14. During the etching process, a plurality of negative charges 20 and a plurality of positive charges 25 build on the surface of the photoresist layer 16. FIG. 1b illustrates a cross-sectional view of the wafer 10. A gate 22 of a transistor (not shown) includes a gate oxide layer 24 located between the gate 22 and the substrate 12. The gate 22 and the gate oxide layer 24 are disposed in a first via or trench 26. A negative charge 20 has built up around the first via or trench 26 during etching. A second via or trench 28 is disposed near the first via or trench 26 and has positive charge 25 that has built up around the second via or trench 28 during etching. The difference in the charge build up causes a voltage potential between the resist around the first via or trench 26 with respect to the second via or trench 28. This results in current flowing through the first via or trench 26 to the second via or trench 28. The current flow causes damage to the gate oxide layer 24 resulting in device defects. In view of the above, improvements are needed to mitigate the aforementioned problems.
The present invention provides for a wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.
Ideally, this layer can serve as an antireflective (arc) as well, eliminating the need for a separate arc layer. Since this layer conducts, the layer will redistribute charge from a non-uniform plasma etch, preventing current flowing through the wafer features. Alternatively, the conductive layer may be grounded or held at a fixed potential by attaching a contact to a peripheral edge of the wafer and attaching the contact to a fixed potential. Additionally, a contact can be formed from the conductive layer to the top surface of the wafer and attached to a fixed potential. A contact can be also formed that attaches the underlying substrate layer to the conductive layer. The substrate layer acts as a ground to hold the conductive layer at a fixed potential. The contact can be coupled to a plate holding the substrate layer, which may act as a ground for the conductive layer. Preferably, the conductive layer will be both conducting and removable. One example of a film meeting this criteria is using a titanium nitride (TiN) antireflection coating (ARC). Other possible conductive layers include titanium, tantalum and tantalum nitride.
One aspect of the invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. The method includes the steps of providing a substrate having an insulating layer and forming a conductive layer over the insulating layer. A photoresist layer is provided over the conductive layer and the photoresist layer is developed exposing portions of the conductive layer. The exposed portions of the conductive layer and underlying insulating layer are etched to form at least one opening extending to the substrate.
Another aspect of the present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. The method includes the steps of providing a substrate having an insulating layer and forming a conductive antireflective layer over the insulating layer. A photoresist layer is provided over the conductive antireflective layer. The photoresist layer is developed exposing portions of the conductive anti reflective layer. The exposed portions of the conductive antireflective layer are etched exposing portions of the insulting layer. The exposed portions of the insulating layer are etched to form a via. The photoresist layer is stripped and the conductive material layer is removed. The via is then filled with a contact material layer.
Yet another aspect of the present invention provides for a method for fabricating interconnecting lines and vias in a layer of insulating material. The method comprises the steps of providing a substrate having an insulating layer and forming a titanium nitride antireflective layer over the insulating layer. A coupling contact is formed from the antireflective layer to the substrate. A photoresist layer is provided over the titanium nitride antireflective layer and the photoresist layer is developed exposing portions of the antireflective layer. The exposed portions of the titanium nitride antireflective layer are etched exposing portions of the insulating layer. The exposed portions of the insulating layer are etched to form a via. The photoresist layer is stripped and the conductive material layer is removed. The via is then filled with a contact material layer. The contact material layer covers the insulating layer. The contact material layer is then polished back.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.